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 ESDLIN1524BJ
TRANSILTM diode for ESD protection
Features

Max peak pulse power 160 W (8/20 s) Asymmetrical bidirectional device Stand-off voltage: 15 and 24 V Low clamping factor VCL/VBR Complies with the following standards : - IEC 61000-4-2 level 4 (> 15 kV air discharge, > 8 kV contact discharge) - IEC 61000-4-5; Ipp= 3 A (8/20 s) - HBM MIL STD 833, class 3 (> 4 kV) Low Leakage current
2 1
SOD-323
Configuration
Description
The ESDLIN1524BJ is an asymmetrical TRANSIL diode designed specifically for protecting one automotive LIN bus line against electrostatic discharge (ESD). The SOD-323 is a very small package which allows space saving on high density printed circuit board . Transil diodes provide high overvoltage protection by clamping action and have instantaneous response to transient overvoltages. Table 1.
Symbol PPP Tstg Tj TL
1
21
2
Pin 1 2
Description Cathode 1 (15 V reverse stand-off voltage) Cathode 2 (24 V reverse stand-off voltage)
Absolute maximum ratings (limiting values) Tamb = 25 C
Parameter Peak pulse power dissipation 8/20 s Storage temperature range Operating junction temperature range Maximum lead temperature for soldering during 10 s
(1)
Value Tj initial = Tamb 160 -65 to +175 -40 to 150 260
Unit W C C
1. For a surge greater than maximum values, the diode will fail in short-circuit
Table 2.
Symbol ESD
ESD Maximum ratings
Parameter Electrostatic discharge capability Conditions IEC 61000-4-2 (contact discharge) HBM MIL STD 833 Value 23 10 Unit kV
TM: TRANSIL is a trademark of STMicroelectronics.
September 2006
Rev 2
1/7
www.st.com 7
Characteristics
ESDLIN1524BJ
1
Table 3.
Symbol VRM VBR VCL IRM IR IPP C
Characteristics
Electrical characteristics (Tamb = 25 C)
Parameter Stand-off voltage Breakdown voltage Clamping voltage
V C LV B R V R M I R IM R IM R I R V V R MV B R V C L I I PP
Leakage current @ VRM Breakdown current @ VBR Peak pulse current Junction capacitance
I PP
IRM @VRM Types nA V Typ Max ESDLIN1524BJ(15V) ESDLIN1524BJ(24V)
1. Pulse test: tp < 50 ms 2. VR = 0 V, F= 1 MHz 3. VBR = T x (Tamb -25) x VBR(25 C)
VBR @ IR (1) V mA Min Typ Max 5 5
VCL max @ IPP 8/20 s V 25 40 A 1 1 V 35 50 A
C (2) pF Typ Max
T(3) 10-4/C Max 8.8
1 1
50 50
15 17.1 18.9 20.3 24 25.4 27.8 30.3
5 16 3 20
9.6
Figure 1.
Relative variation of peak pulse power versus initial junction temperature
Figure 2.
Peak pulse power versus exponential pulse duration
PPP[Tj initial] / PPP [Tj initial=25C]
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 175 TJ(C)
PPP(W)
1.E+03
Tj initial =25 C
1.E+02
tP(s) 1.E+01 1 10 100
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ESDLIN1524BJ
Characteristics
Figure 3.
Junction capacitance versus line voltage (typical values), 15 V side
Figure 4.
Junction capacitance versus line voltage (typical values), 24 V side
C(pF)
20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VLINE(V)
15 V side F=1 MHz VOSC=30mVRMS TJ=25C
C(pF)
20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 20 22 24 VLINE(V)
24 V side F=1 MHz VOSC=30 mVRMS TJ=25 C
Figure 5.
Clamping test conditions and results
2 TEST BOARD 1kV ESD Air discharge Voltage probe Ground plane ESD test configuration V 500
3/7
1
V:20V/d
t: 50 ns/d
V:20V/d
t: 50 ns/d
Remaining voltage after +1 kV ESD voltage waveform (IEC 61000-4-2 conditions)
Remaining voltage after -1 kV ESD voltage waveform (IEC 61000-4-2 conditions)
Placement and PCB layout recommendations
ESDLIN1524BJ
2
Placement and PCB layout recommendations
Figure 6. illustrates recommendations for the placement and layout of the PCB for optimum benefit of the ESDLIN1524BJ. Figure 6. Placement and PCB layout recommendations
LIN Node
Voltage regulator
Vbat
Connector
Gnd
MCU
LIN
24
LIN Transceiver
15
ESDLIN1524BJ located as close as possible to the connector
With Ground wire
Vbat
With Ground plane
Vbat
Connector
LIN
Connector
LIN
GND
GND
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ESDLIN1524BJ
Ordering information scheme
3
Ordering information scheme
ESDLIN 15
ESDLIN protection Stand-off voltage 1 15 = 15 V Stand-off voltage 2 24 = 24 V Bidirectional Package J = SOD-323
24
B
J
4
Package information
Table 4. SOD-323 dimensions
Dimensions
H b E A1
Ref.
Millimeters Min. Max. 1.17 0 0.25 0.1 1.52 1.11 2.3 0.1 0.1 0.1 0.44 0.25 1.8 1.45 2.7 0.46 0.41 0
Inches Min. Max. 0.046 0.004 0.017 0.01 0.071 0.057 0.106 0.02 0.016
A A1
D A
b c
0.01 0.004 0.06 0.044 0.09 0.004 0.004
c
Q1
D E H
L
L Q1
5/7
Ordering information Figure 7. SOD-323 footprint (dimensions in millimeters)
3.20
ESDLIN1524BJ
0.54
1.06
1.08
1.06
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5
Ordering information
Part number ESDLIN1524BJ Marking 24 Package SOD-323 Weight 5 mg Base qty 3000 Delivery mode Tape and reel
6
Revision history
Date 28-Aug-2006 22-Sep-2006 Revision 1 2 Initial release. Added Figure 6 Placement and layout recommendations. Changes
6/7
ESDLIN1524BJ
Please Read Carefully:
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